1. Field of the Invention
This invention relates to digital to analog converters, and more particularly to digital to analog converters which utilize a pulse width modulation or other averaging technique.
2. Description of the Prior Art
Digital to analog converters, including digital to analog converters utilizing pulse width modulation techniques, are well known in the prior art. One such pulse width modulation digital to analog (D/A) converter is shown in the schematic diagram of FIG. 1a. Digital to analog converter 9 includes latch 1 which is capable of storing a digital word containing a plurality of binary digits (bits). Digital to analog converter 9 also includes binary counter 2. In the embodiment shown in FIG. 1a, the latch 1 and binary counter 2 are nine bits wide. In other words, latch 1 is capable of receiving a binary input word formed of a plurality of nine bits A0 through A8.
During the operation of the prior art digital to analog converter 9 of FIG. 1a, a nine bit binary signal A0 through A8 is applied to the input leads of latch 1. A high LOAD signal is applied to the load input lead of latch 1, thus storing bits A0 through A8 in latch 1. These bits A0 through A8 form a nine bit word which define the digital representation of the analog voltage to be generated. This nine bit word is available as output bits 00 through 08 from latch 1. These bits 00 through 08 are loaded into counter 2 on the positive going transition of the LOAD signal, thus presetting the count of counter 2 to the nine bit binary word representing the analog voltage to be generated. This high signal LOAD is generated on the negative going transition of the LOAD signal which is connected to the load input lead of Counter 2 via inverter 27.
Upon each positive transition of a clock signal COUNT (shown in FIG. 1b) applied to the COUNT input lead of counter 2, the count provided by counter 2 is decremented by one until a count of 000000000 is reached. When a count of 000000000 is stored in counter 2, the count remains fixed at 000000000, even upon receipt of further positive going COUNT clock signals. The count of counter 2 is provided as output signals B0 through B8 which are applied to the input leads of NOR gate 3, which generates on its output lead 3-1 a signal which is a logical one only when the binary counter B0 through B8 provided by counter 2 is equal to 000000000. For all other counts B0 through B8 of counter 2, the output signal on lead 3-1 will be a logical zero. The output signal from NOR gate 3 is applied to the SET input lead of RS flip flop 4. RS flip flop 4 is reset on the positive going edge of the LOAD clock signal (applied to the RESET input lead of flip flop 4) such that its output signal Q is a logical one. Similarly, RS flip flop 4 is set upon receipt of a positive going signal on lead 3-1 such that the output signal Q from flip flop 4 is a logical zero. Accordingly, at the beginning of the digital to analog conversion process, when a nine bit binary word representing the analog voltage to be generated is stored in latch 1, RS flip flop 4 is reset such that its output signal Q is high (logical 1). Upon each pulse of clock signal COUNT the count of counter 2 is decremented by one. After a given number of COUNT clock cycles, the count of counter 2 is 000000000, at which time the output signal available on lead 3-1 of NOR gate 3 is equal to a logical one, thus setting the Q output signal of flip flop 4 to a logical zero. The output signal Q of RS flip flop 4 is shown in FIG. 1c. As shown in FIG. 1c, the period of one digital to analog conversion operation is equal to the reciprocal of the frequency F.sub.LOAD of clock signal LOAD. Similarly, the time during which the Q output signal from flip flop 4 is a logical one is shown as time W1. This time W.sub.1 is dependent on the initial binary word A0 through A8 stored in latch 1 which represents the analog voltage to be generated. Thus, when a relatively high analog voltage is to be generated, a relatively large binary word A0 through A8 will be stored in latch 1, thus causing a relatively large number of COUNT clock pulses to decrement the count of counter 2 to a value of 000000000, thereby providing a relatively large time W.sub.1 during which the output signal Q of flip flop 4 is high. Conversely, if a relatively small analog voltage is to be generated, a relatively small binary word A0 through A8 will be loaded into latch 1, thus causing a relatively few COUNT clock pulses to cause the count of counter 2 to decrement to 000000000, thereby providing a relatively small time W.sub.1 during which the output signal Q of flip flop 4 is high.
In one embodiment as shown in FIG. 1a, the frequency F.sub.COUNT is equal to 2.sup.9 times the frequency F.sub.LOAD, when the binary word A0 through A8 is comprised of nine bits. To state this relationship more generally, for an N bit binary input word, EQU F.sub.COUNT =2.sup.N F.sub.LOAD,
where
F.sub.COUNT =the frequency of the clock signal applied to the COUNT input lead of counter 2, and PA1 F.sub.LOAD =the frequency of the clock signal applied to the LOAD input lead of latch 1 and to the RESET lead of flip flop 4.
To provide greater resolution in the generated analog signal, a greater number of bits must be used to define the analog voltage to be generated, and thus latch 1, counter 2 and NOR gate 3 must be capable of performing their operations on this greater number of bits. For example, in order to provide a digital to analog converter having twice the resolution of the nine bit digital analog converter of FIG. 1a, a ten bit digital to analog converter must be provided wherein latch 1 is capable of receiving and storing a ten bit word representing the analog voltage to be converted, counter 2 is capable of being preset to the ten bit word stored by latch 1, and NOR gate 3 is capable of performing a NOR operation on the ten output bits from counter 2. Naturally, for a ten bit digital to analog converter, the frequency of F.sub.COUNT =2.sup.10 F.sub.LOAD. While it appears rather straightforward to increase the resolution of a digital to analog converter by providing that the digital to analog converter is capable of handling the required number of bits, the frequency of the COUNT signal limits the extent to which this can be done. For example, in many typical digital to analog converter applications, the frequency of the LOAD signal is required to be on the order of 10 Kilohertz, thus allowing 10,000 digital to analog conversions per second. This large number of digital to analog conversions is required in order to generate an analog signal which varies rather rapidly with time. Thus, for a LOAD signal with a frequency of 10 KHz, the resolution of the DAC is limited to nine bits since 2.sup.9 .multidot.10 KHZ=5.12 MHZ. It is well known that by utilizing a sampling frequency F.sub.LOAD, the output signal will contain a noise component of frequency F.sub.LOAD and its harmonics. When utilizing F.sub.LOAD =10 KHz, the result is a very strong 10 Kilohertz noise component. In order to eliminate this 10 Kilohertz noise component and its harmonics, a significant amount of filtering is required. Furthermore, if it is desirable to retain the signal components near 5 Kilohertz, a very selective notch filter is required. Such filters are capable of being manufactured using well known principles, although it will be appreciated by those of ordinary skill in the art that such filters may require a large number of stages, a large number of components, and thus increased cost and device complexity. Another method for reducing the undesirable effect of sampling noise is to increase the frequency of the LOAD signal to a point where sample noise is not within the frequency band of interest. Thus, for example, in a digital to analog converter whose output signal is in the human audible range rather than using an F.sub.LOAD equal to 10 KHz, the converter can be constructed wherein F.sub.LOAD equals 40 KHz, thereby providing an output noise component of 40 KHz, and its harmonics well beyond the hearing range of most humans.
It is often desirable to implement a digital to analog converter as a monolithic integrated circuit device formed on a single piece of semiconductor material, and often as a subsystem of a much larger system formed on a single piece of semiconductor material. Many semiconductor circuits cannot operate at a frequency much greater than about 5 MHz. Thus, for a digital to analog converter capable of providing approximately 40,000 digital to analog conversions per second, the resolution is limited to approximately seven bits in that, for a seven bit resolution, the frequency F.sub.COUNT =2.sup.7 F.sub.LOAD =(128)(40 KHz)=5.12 MHz. Thus, such prior art digital to analog converters are limited as to their resolution, or as to their repetition frequency (i.e. the number of digital to analog conversions per second). For a given operating speed, if a higher resolution is desired, the repetition frequency must decrease, thereby requiring additional filtering of the analog voltage which is generated and providing a more poorly defined analog output signal due to the lower sampling rate.
Another type of prior art digital to analog converter utilizing a pulse width technique is described in U.S. Pat. No. 4,117,476 issued Sept. 26, 1978 on an invention of Koyanagi. Koyanagi utilizes a plurality of flip flops and logical gates to implement a pulse width digital to analog converter.
Of importance, in these prior art digital to analog converters, the output signal contains a noise component at the frequency of the input sampling rate and its harmonics.